FIELD OF THE INVENTION
The invention lies in the electronics field. Specifically, the present invention relates to a clock signal generator in which the duty ratio of the clock signals produced is programmable.
A clocked logic circuit has been disclosed, for example, in U.S. Pat. No. 4,719,365 to Misono (European EP 0 183 875 A). That device, however, is not suitable for producing clock signals of the type to which the invention pertains.
Clock signal generators of the known type are used, amongst other things, for controlling master/slave registers and the like, for example. Master/slave registers contain two storage elements connected in series, namely a so-called master store and a so-called slave store, which are controlled using two mutually different clock signals. More precisely, the first clock signal determines the instant at which any data present are transferred to the master store, and the second clock signal determines the instant at which data stored in the master store are transferred to the slave store.
Data may generally be transferred from the master store to the slave store only when the clock signal controlling the master store has assumed a state which prevents data from being written to the master store. If this were not the case, the data stored in the master store would still be able to change while being transferred to the slave store, which should normally be avoided if possible.
Consequently, the first clock signal and the second clock signal must never simultaneously be in a state which allows data to be transferred to the respective store. This can be achieved, for example, by generating the second clock signal by inversion of the first clock signal, so that the clock signals have essentially complementary waveforms. Clock signals generated in this manner are, in principle, suitable for controlling master/slave systems and the like.
However, on account of signal delay times, component tolerances, and the like, the above-mentioned overlaps in the signal waveforms, which are to be avoided, may nevertheless occur with the clock signals. This is undesirable and a serious problem, particularly at high clock frequencies and with stores responding at a correspondingly fast rate.
In order to avoid this, it is possible to process the mutually inverse clock signals in such a manner that a so-called overlap-free phase is imposed between the respective active phase of one clock signal and the subsequent active phase of the other clock signal. Both clock signals are in an inactive phase, for example a low-level phase, during the overlap-free phase.
Such an overlap-free phase can be provided (while maintaining the respective clock frequencies) by appropriately shifting the rising and/or falling edges of the first and/or of the second clock signal. This can be achieved using appropriate delay stages. See, for example, U.S. Pat. No. 5,453,707 to Hikichi (European EP 0 606 912 A).
Even though the use of such clock signals matched to the supposed conditions generally permits master/slave registers and the like to be driven considerably more reliably, there are nevertheless repeatedly cases, in practice, in which master/slave registers or the like cannot be operated correctly, despite the provision of the measures. This necessitates research into the cause and requires the relevant circuit or its affected circuit parts to be redesigned, which processes are frequently very extensive and correspondingly costly.
The same also applies to the case where the duty ratio of the clock signals used is responsible for the master/slave registers or the like operating incorrectly. In that case, too, matching to the supposed conditions does not automatically lead to the correct operation of the master/slave registers.